ARM Senior Architect High Speed Interface 

United States, Texas, Austin 

485528212

We are looking for a Senior Architect – High Speed Interface to own the definition and deployment of high-speed interconnects in our System designs. This role focuses on die-to-die (D2D) interconnects and off-chip SerDes solutions. You will be responsible for selecting and optimizing interface IP—including PHY and controller subsystems—for use in advanced multi-die and chiplet solutions.

You will evaluate vendor IP, guide architecture tradeoffs, and ensure efficient integration of high-speed interfaces. This includes assessing how integration affects power grids, silicon area, and thermal performance. You will also help align teams across silicon, system, and packaging domains!

• Drive the selection of high-speed interfaces (e.g., UCIe, HBI, proprietary D2D, PCIe, Ethernet) based on system-level PPA and integration complexity.
• Maintain structured comparisons of PHY/controller IP vendors, collaborating with the Technology Team on roadmap alignment and integration readiness.
• Analyze PHY choices for impacts on power delivery, bump congestion, and thermal hotspots.
• Lead PHY characterization and bench review sessions with third-party IP partners.
• Define integration guidelines across PHY, controller, and CMN to ensure robust die-to-die connectivity.
• Lead multi-disciplinary forums to align interface selection and integration tradeoffs across SoC, packaging, and IP teams.
• Collaborate with packaging teams to assess substrate/interposer capabilities and their effects on PHY performance.
• Participate in post-silicon validation of high-speed interfaces, including SI analysis, issue triage, and protocol debugging.
• Contribute to interface roadmaps, architectural documents, and executive presentations.

• 10+ years in interface architecture, high-speed PHY/controller assessment, or related SoC integration.
• Deep knowledge of SERDES design, architecture, equalization, clocking, and signal integrity.
• Familiarity with coherent protocols (e.g., CHI) and their integration implications.
• Proven experience with third-party or in-house PHY/controller IP evaluation.
• Expertise in die-to-die interfaces and packaging-aware integration tradeoffs.
• Strong architectural judgment balancing layout, power, and system performance.

• Experience with chiplet-based SoCs and 2.5D/3D packaging.
• Knowledge of UCIe, HBI, BoW, Ethernet, and related standards.
• Exposure to DTCO and PHY floor planning impacts.
• Understanding of SoC power grid and macro placement strategies.
• Strong collaboration and influence across engineering teams.