Intel SoC High-Speed I/O PHY Architect 

United States, Texas 

928459664

Key Responsibilities
Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx (e.g., eUSB2, USB3, USB4), Display, MIPI (D-PHY, C-PHY, M-PHY), Ethernet, and TSN.
Collaborate with platform and product architects to analyze requirements and define critical performance, power, and area specifications to ensure the success of our products.
Conduct technical evaluations of both internal and external PHY IPs, analyzing their performance characteristics against product requirements, and ensuring strategic alignment with overall product goals.
Define detailed IP requirements, lead vendor engagement, and make strategic IP selection recommendations based on technical feasibility, cost-effectiveness, and long-term roadmap alignment.
Proactively research and evaluate emerging high-speed I/O technologies, industry trends, and evolving standards.
Identify and champion opportunities to incorporate these advancements into our product roadmap, enhancing performance, power efficiency, and feature sets, and positioning our products for competitive advantage.
Create clear and comprehensive architecture specifications and rigorous integration guidelines.
Provide review and constructive feedback on related architectural specifications to ensure alignment with overall SoC goals.
Serve as a technical lead in the post-silicon debug and validation of high-speed I/O interfaces, leading taskforces and driving the resolution of complex issues.
Oversee the validation process to ensure seamless and high-quality implementations.Additional Skills

• Demonstrated strategic acumen with proven effectiveness in collaborating with senior technologists and business leaders across organizational boundaries.
• Demonstrated ability to network with and influence a broad range of stakeholders
• Strong technical leadership and communication skills

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• BS with 9+ years of experience in Electrical/Computer Engineering or related field
• 6+ years of SerDes experience
• Prior hands-on experience in High-Speed IO PHY Architecture and Design.
• Strong knowledge in the interoperability of HSIO PHYs within the PCIe, SATA, Ethernet, USB2, USB3, USB4, Display or MIPI IO Controller subsystems

• High familiarity with Industry trends within the HSIO domain and ability to map them to Intel roadmap/products and segment strategies
• We look forward to welcoming a dynamic and innovative High-Speed I/O (PHY) Architect to our team. Apply now and be a part of shaping the future of our client SoC technology

We look forward to welcoming a dynamic and innovative High-Speed I/O (PHY) Architect to our team. Apply now and be a part of shaping the future of our client SoC technology

Experienced HireShift 1 (United States of America)US, California, FolsomUS, California, Santa Clara
Position of Trust

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