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Google High Speed Interface Design Engineer Silicon Taiwan, New Taipei 363755345
Today
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
- 8 years of experience with Serializer/Deserializer (SERDES) key sub-blocks design, such as transmitter, receiver, phase-locked loops, clock and data recovery circuit.
- Experience with lab bring-up, silicon characterization, and debug of mixed-signal IPs.
- Experience with CMOS design, layout and validation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
- Experience with highly scaled CMOS (FinFET) design, layout and validation, low power design techniques such as dynamic voltage or frequency scaling and creating behavioral models of analog circuits in SystemVerilog or VerilogA and analysis of system level tradeoffs.
- Experience covering the full product lifecycle: specification, architecture, design, and productization of PHYs (Physical Layer Protocols).
- Familiarity with high speed SERDES sub-blocks such as Transmitter, PLL, CTLE, DFE, Sense Amplifier and CDR.
- Familiarity with high speed IO specifications like PCIE, MIPI CDPHY, UCIE and LPDDR.
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