Job Description:In this position, you will be converging Mixed Signal APR blocks in Intel SoC Client product or Test Chip.
- You will work closely with RTL, Circuit and Mask Designers, deep dive into analog IP integration and troubleshoots a wide variety of design issues and applies proactive intervention.
- Requires good knowledge and practical application methodologies in physical design. Innovation and efficiency improvement in the day to day execution is an added advantage.
- Works include but not limited to synthesis, partition level floorplan, auto place and route, RC extraction and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, static timing and reliability analysis, clock generation, auto-place and route algorithms, floor planning, IP integration, and verification.
Qualifications:Bachelor/Masters of Science/Engineering degree inElectronic/MicroelectronicsEngineering or equivalent with preferable 1-5 years of working experience in structural design or related field.
Additional qualifications include:
- Knowledgeable in digital logic design, VLSI CMOS custom circuit design
- Strong programming skills in C/C++, or Perl/TCL, Python
- Good communication and strong analytical skills
- Strong team player
Experienced HireShift 1 (Malaysia)Malaysia, Penang