ISCP MIP MYS is seeking Mixed-signal design engineers to join our talented and vibrant team. You will be directly involved in delivering next-generation LPDDR6/DDR6 PHY or Die2Die Interconnects PHY designs for SOC application on Intel leading process node. Key Responsibilities include but not limited to: � Design and development of mixed-signal circuits such as High Speed TX and RX, Various type of compensation circuitry, equalizers, DLL, clocking circuitry such as duty cyclePreferred Qualification: � Good understanding of IC design for yield, fabrication and production challenges � Expose to industry EDA standard tools for analog design such as Cadence ADE, Spectre, AMS verification, FEV, StarRC etc.� Strong written and oral communication skills� BSEE with relevant education syllabus focus should include integrated circuit design and fabrication processCollege GradShift 1 (Malaysia)Malaysia, Penang