Honeywell Lead Mask/Layout Design Tech 

United States 

418061637

The future is what you make it.

That means changing the way we fly, fueling jets in an eco-friendly way, keeping buildings smart and safe and even making it possible to breathe on Mars.

Join the engineering team at Honeywell that designs, verifies, integrates, and tests complex integrated circuit products that enable systems development for deployment in space. Honeywell’s integrated circuit wafer foundry produces parts for satellites, space probes, defense, and other novel applications. You will develop radiation hardened ASIC Design platform capabilities in support of the organization's business strategies. You will be responsible for interfacing with internal and external Honeywell ASIC-capability development teams and translating our mixed signal designs and digital library cells using Cadence and Mentor tools for physical design and verification. You will work closely with world class hardware and mixed signal-ASIC tool flow development engineers during planning, requirements and architecture, design, test, and integration phases.

Key Responsibilities

• Deliver high quality layout that conform to all design requirements.
• Provide accurate scheduling and planning to meet project milestone deadlines.
• Design reviewing and analyzing floorplans with the circuit designer.
• Negotiate layout tradeoffs with the circuit designer.
• Be able to recognize issues in schematic or layout and work with engineers to resolve.
• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
• Run all verifications including DRC, LVS, ERC, ANTENNA, etc.
• Support and assist in tape out, mask generation and orders.
• Support tool and process enhancements as needed to ensure successful design fabrication.
• Prepare Documentation
• Mentor and Lead and mentor all aspects of our mask design process for assigned programs and to contribute as a SME to other programs and engineers as needed.

Tools We Use:

• Cadence PDK and Siemens-EDA physical verification for library item development
• Synopsys place-and-route system suite of tools

YOU MUST HAVE

• High School Diploma
• 5 years of experience in with Cadence and Mentor/Siemens tools
• Ability and willingness to work on-site at the Honeywell Plymouth, MN facility 3 days per week (possible on-site in Redmond WA, 3+)

WE VALUE

• Associate or technical degree in Electrical Engineering, Semiconductor Physics, or a related field
• Degree focused on IC cell design and layout, or similar field
• Experience in cell design layout and verification for ASIC library utilization
• Experience or interest in memory design layout and verification
• I/O layout design experience and ESD design experience or interest
• Knowledge of Linux OS, scripting languages such as Perl

We offer a full benefits package that includes medical, dental, vision, 401(k), flexible vacation and education assistance. Benefits provided may differ by role and location.

• JOB ID: HRD236625
• Category: Engineering
• Location: 12001 State Highway 55,Plymouth,Minnesota,55441,United States
• Nonexempt
• Due to US export control laws, must be a US citizen, permanent resident or have protected status.