Qualcomm SRAM Mask Layout Designer 

India, Karnataka, Bengaluru 

411030445

Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

• 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics.

Minimum qualifications

● 7+ years of experience and a high school diploma or equivalent

● OR 5+ years experience and BS in Electrical Engineering

● OR 3+ years experience and MS in Electrical Engineering

● Direct experience with custom SRAM layout

● Experience in industry standard custom design tools and flows.

● Knowledge of leading-edge FinFET and/or nanosheet processes (5nm or newer).

● Experience in Layout design of library cells, datapaths, memories in deep

sub-micron technologies.

● Knowledge of all aspects of Layout floorplanning and hierarchical assembly.

● Knowledge of Cadence Virtuoso and Calibre LVS/DRC.

Preferred qualifications

● Good understanding of device parasitics and reliability considerations during

● Good understanding of critical circuits and layout styles.

● Ability to write Skill code for layout automation.

● Knowledge of improving EMIR in layout.

● Good communication skills to work with different teams to accurately describe

issues and follow them through for completion.

Roles and Responsibilities

● Design layout for custom memories and other digital circuits based on provided

● Read and interpret design rule manuals to create optimal and correct layout.

● Own the entire layout process from initial floorplanning to memory construction to

physical verification.

● Use industry standard verification tools to validate LVS, DRC, ERC etc.

● Interpret the results from the verification suite and perform layout fixes as

● Provide layout fixes as directed by the circuit design engineers.

● Work independently and execute memory layout with little supervision.

● Provide realistic schedules for layout completion.

● Provide insight into strategic decisions regarding memory layout and

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.