APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Develop block-level test benches for RTL simulation and implement such test plans using System Verilog. Write assertions, and add function coverages for UVM testbenches. Maintain regressions, debug any failures and improve current flow by Python scripting. Add new testcases for existing test plans and enhance existing scoreboards using System Verilog and Python. Develop Models based on the design doc and metrics. Develop Model test plans using C++ and Python. Ensure a bug-free first silicon for part of the cellular modem SoC / IP. Develop detailed test and coverage plans based on the micro-architecture. Develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling, and debugging of test failures. Track and report DV progress using a variety of metrics, including bugs and coverage. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location.