המקום בו המומחים והחברות הטובות ביותר נפגשים
Apple Design Verification Engineer United States, California, Cupertino 312416842
12.05.2025
- Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field.
- Education and/or experience must include the following skills:
- Using Verilog and SystemVerilog for constrained random test development
- Developing test plan and coverage plan
- Using C/C++ for reference model and checker development
- Perl, Python and TCL scripting for regression automation
- Knowledge of Digital Electronics and RTL design concepts
- Knowledge of simulators and waveform viewers for running tests and debugging digital designs
- Writing System Verilog Assertions (SVA) for simulations-based and formal verification
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