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What you’ll be doing:
As a key member of our design team, you will be responsible for the micro-architecture and design implementation of GPU memory subsystem modules.
Make architectural trade-offs based on features, performance requirements and system limitations, and deliver a fully verified design by working closely with verification engineers.
Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design.
Collaborate with architects, verification engineers, software engineers, and physical design engineers to accomplish your goals.
What we need to see:
Bachelors or Master’s Degree in Electrical Engineering or Computer Engineering, or equivalent experience.
At least 3 years of relevant work or research experience.
Highly proficient in logic design, Verilog and/or System-Verilog, with a good understanding of Computer Architecture and Digital Systems design.
A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis, ECO, and post silicon debug.
Strong interpersonal skills and an excellent teammate.
Ways to stand out from the crowd:
Prior design experience with arbiters, scheduling, synchronization, bus protocols, interconnect networks and/or switches.
Familiarity with architecture concepts and implementation of arbitration policies, interconnection routing policies/deadlock avoidance, virtual channels.
Interest or have prior experience in efficiency enhancement, such as, flow development and code generator.
Good debugging and analytical skills.
You will also be eligible for equity and .
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