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Intel DFT Design Engineer United States, Colorado, Fort Collins 247010846
Who You Are
Your job responsibilities will include but not limited to:
Developing the logic design, register transfer level (RTL) coding, simulation, and DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vectormemory reduction goals as well as design integrity for physical implementation.
Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.
Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
Minimum Qualifications
Bachelor’s degree in Computer or Electrical Engineering, or a related field with a year of related experience OR Master's degree in Computer or Electrical Engineering, or a related field
1 year experience with test architecture
Preferred Qualifications
6+ months experience with:
GLS to resolve stuck-at and at-speed test scenarios
ATPG coverage analysis
EDT configuration setup
TCL, Python, Perl and/or C++ programming
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