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Intel IFS Design Test DFT Engineer United States, Oregon, Hillsboro 647004275
Who You Are
As a DFT Engineer in IFS you will:
Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Follows secure development practices to address the security threat model and security objects within the design.
Works with IP providers to integrate and validate IPs at the SoC level.
Drives quality assurance compliance for smooth IPSoC handoff.
The chosen candidate will also have the following skills in addition to the qualifications listed below:
Willingness to present information and influence technical groups (SP) Excellent communication skills.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork, classes, research and or relevant previous job and or internship experiences.
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Math.
3+ months experience with Design for Test Solutions gained from internship or coursework.
Preferred Qualifications
Post graduate degree Electrical Engineering, Computer Engineering Computer Science, or in a related field
2+ Years experience with Tessent DFT solutions (e.g., Scan, TestKompress, Memory BIST/BISR, Logic BIST, iJTAG etc.)
2+ Years experience in optimizing tools/flows/methods for DFT insertion and validation.
2+ Years experience with the SoC development process (e.g. synthesis, static timing
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