

What you will be doing:
Developing comprehensive FVtestplandocuments.
Identifying key behaviors for verification of DUT and creating a verification plan.
Developing verification environment including environment assumptions, assertions and cover properties in context of the verification plan.
Applying various FV techniques to proof correctness of digital designs.
Debugging RTL to identify failure scenarios.
Developing scripts to automate the verification process.
Review formal setups and proofs with design and verification teams.
What we need to see:
BS, MS, or Ph.D. in CS/CE/EE/Mathematics or equivalent experience.
Strong analytical skills to solve difficult problems.
Knowledge/Experience in formal verification techniques.
Strong knowledge of architectures of CPU/GPU designs and digital logic.
Understanding of abstraction techniques for effective verification.
Hands-on experience with HDLs such as Verilog / System Verilog.
Ability to understand RTL quickly.
Understanding of temporal logic assertions.
Preferable experience with Formal Verification Tools (eg. Jasper, IFV, SMV, SPIN)
Excellent communication skills with ability to work with team members and collaborate effectively.
You will also be eligible for equity and .
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