What you'll be doing:
In this position, you will be responsible for verification of memory subsystem or coherent high speed interconnect design, architecture, golden models and micro-architecture using advanced verification methodologies.
As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation and silicon verification teams to accomplish your tasks.
What we need to see:
Completing or recently completed a Bachelors or Masters Degree (or equivalent experience)
Minimum 6 months experience in architecting test bench environments for unit level verification.
Exposure to verification using random stimulus along with functional coverage and assertion-based verification methodologies.
Prior Design or Verification experience of dynamic memory controllers or coherent high speed interconnects.
C++ programming language experience, scripting ability and an expertise in System Verilog.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Strong debugging and analytical skills.
Strong communication and interpersonal skills are required.
You will also be eligible for equity and .
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