Fortinet Senior Principal ASIC Design Engineer 

United States, California, Sunnyvale 

123364215

You will play a principal role in developing next-gen SOC architecture, perform IP integration, chip level RTL design & verification and lead low power design methodology. Candidate must be able to work with self-motivation and deliver on commitments with challenging schedules, lead design teams through various phases of ASIC design process including RTL design, chip level verification, coverage analysis, synthesis and STA. Candidate must possess solid knowledge in SOC design techniques, analog IPs, high speed IO protocols, CPF/UPF power design flow and lint/CDC tools.

Job Responsibilities:

Lead architecture design to shape micro-architecture of next-generation SOC FortiASIC.Design implementation using Verilog HDL and synthesis.

Job Requirements:

Experienced in design and implementation of complex multi-million gate SOCs.
Familiarity with ARM subsystem, SMP multi-socket cache coherency.
Familiarity with high speed IP protocols such as PCIe5 and DDR5.
Preferred experience in chiplet multi-die system-in-package design.

Strong experience designing digital circuits using Verilog HDL.
Strong experience in formal verification of digital design.
Fluent in C, C++, assembly and scripting languages.
Excellent communication skills.

Education Requirements:

MS & BS in Electrical Engineering or related field with 10+ years of SOC ASIC design experience.

Wage ranges are based on various factors including the labor market, job type, and job level. Exact salary offers will be determined by factors such as the candidate's subject knowledge, skill level, qualifications, experience, and geographic location.