Fortinet Principal ASIC Design Engineer 

United States, California, Sunnyvale 

600602318

Job Responsibilities

• Develop network processing ASIC/FPGA architecture and micro architecture specification
• Design high performance and high quality ASIC/FPGA design from specification to RTL implementation
• Perform ASIC/FPGA verification, lint/cdc, synthesis, timing analysis and IP integration
• Implement network packet processing system using Altera/Xilinx FPGA
• Participate in system/board level bring up, debugging and support

Experience Required

• 8 years or more networking or processor design experience
• Strong track record of ASIC/FPGA design from concept to mass production
• Hands on experience in Verilog HDL coding and verification
• Experience of high performance ASIC/FPGA design from specification to system bring up
• Experience with Altera/Xilinx FPGA architecture, tools and IP portfolio
• Ethernet and TCP/IP networking concept and protocols knowledge
• Knowledge of System Verilog and UVM verification methodology
• Highly motivated, positive, detail oriented and responsible
• Good team player and good communication skills

Educational Requirement

Wage ranges are based on various factors including the labor market, job type, and job level. Exact salary offers will be determined by factors such as the candidate's subject knowledge, skill level, qualifications, experience, and geographic location.