דרושים Physical Design Soc Clock Engineer ב-אינטל ב-United States, San Jose

WHO YOU ARE

Responsibilities include, but are not limited to:

• Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.

• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.

• Replicates, root causes, and debugs issues in the presilicon environment.

• Finds and implements corrective measures to resolve failing tests.

• Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.

• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.

• Maintains and improves existing functional verification infrastructure and methodology.

• Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages and proliferates to future products.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 1+ years of relevant experience

— or —

Master’s degree in the same fields

Relevant work experience should be of the following:

• Experience with UVM
• Experience with System Verilog
• Experience with Design Verification
• Experience with Computer Architecture
• Experience with Hardware Verification

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

College GradShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 90,890.00 USD - 170,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/25/2026

Job Description:

Responsibilities include, but are not limited to:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.

• Participates in the definition of architecture and microarchitecture features of the block being designed.

• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.

• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Follows secure development practices to address the security threat model and security objects within the design.

• Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

This is an entry level position and will be compensated accordingly.

Minimum qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 1+ years' experience withScripting (python, pearl, or other similar programming languages)

— or —

Master’s degree or PhD in the same fields

Preferred qualifications:

• UPF coding.

• Integrating and ensuring IP components within SOC

• Implementing physical connectivity

• Testing and verification

Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.

College GradShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 90,890.00 USD - 170,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 08/31/2026

WHO YOU ARE:

As an IP Logic Design Engineer your responsibilities will include but are not limited to:

• Designing and/or integrating IP for Intel's Custom Silicon solutions.

• You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation.

• Creating a design to produce key assets that help improve product KPIs for discrete graphics products.

• Working with SoC Architecture and platform architecture teams to establish silicon requirements.

• Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.

• Creating micro architectural specification document for the design.

• Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.

• Driving vendor's methodology to meet world class silicon design standards.

• Architecting area and power efficient low latency designs with scalabilities and flexibilities.

• Power and Area efficient RTL logic design and DV support.

• Running tools to ensure lint-free and CDC/RDC clean design, VCLP.

• Synthesis and timing constraints.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience

— or —

Master’s degree in the same fields with 2+ years of relevant experience

— or —

PhD in the same fields.

Relevant work experience should be of the following:

• xperience with complex IP/ASIC/SOC Design Implementation.

• Experience in system and processor architecture.

• Experience with System Verilog/SOC development environment.

Preferred Qualifications:

• Experience in scripting languages (i.e. PERL, TCL, or Python).

• Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).

• Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.

• Experience in leading small team of engineers.

• Experience with Industry standard protocols (i.e. PCIE, USB, DDR, etc).

• Experience with interaction of computer hardware with software.

• Experience with Low power/UPFimplementation/verificationtechniques.

• Experience with Formal verification techniques.

Experienced HireShift 1 (United States of America)Virtual US
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 121,050.00 USD - 227,620.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 08/31/2026

Experienced HireShift 1 (United States of America)Virtual US
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 999.00 USD - 999,999.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 12/23/2025

Job Description:

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Defines SoC or subsystem level clocking targets and drives design teams to achieve these objectives as required.

• Builds simulation models, drives physical implementation, conducts clock analysis, and supports power grid methodologies and implementation.

• Creates scalable flows for clocking infrastructure for better performance and power in the design. Interacts with architecture and IP/SoC design teams to understand clocking requirements and helps them in deciding the right clock distribution methodology based on power and performance requirements.

This position offers work remotely if not co-located at the Fort Collins, CO site.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical / Computer Engineering, Computer Science or in a STEM related field of study with 5+ years of relevant experience

• -OR- Master's in Electrical / Computer Engineering, Computer Science or in a STEM related field of study with 4+ years of relevant experience

Relevant experience should include the following:

• 4+ years of experience hands-on experience across the entire spectrum of RTL to GDS implementation on advance semiconductor technology nodes and specific challenges in clock design.

• 4+ years of experience in Clocking techniques, static timing analysis (STA), clock domain crossing (CDC) checks, jitter/skew analysis and low-power clocking strategies.

Preferred Qualifications:

• Experience with scripting skills in Tcl, Perl, or Python for automation and flow enhancements Understanding of signal integrity, electromigration, and power integrity in the context of clock networks.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/28/2025

You Are

Responsibilities may include but are not limited to:

• As a FC Design Engineer, you will perform constraints management and STA verification.

• You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.

• You will drive timing closure and provide collateral for SOC drops.

Behavioral skills we are looking for:

• Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies.

• Effective team player with continuous learning mindset.

• Strong analytical and problem-solving skills.

• Be willing to balance multiple tasks.

• Self-starter with a collaborative spirit, comfortable asking for help when needed.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• The candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering or similar field with 4+ years' of relevant experience or Master’s Degree in Electrical Engineering, Computer Engineering or similar field with 3+ years' of relevant experience

Preferred Qualifications

• Experience with Static Timing Analysis using PrimeTime

• Experience with Scripting in one or more of the following languages (TCL, Perl, or Python)

• Experience with verification of power crossing ie. VC-static (VC LP), UPF

Experienced HireShift 1 (United States of America)Virtual US
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 10/09/2026

Who You Are

Your responsibilities will include but not be limited to:

• Defines and develops physical clock architecture, drives clocking designs, and creates clocking methodologies and guidelines for IPs or SoCs.

• Designs new clocks modules and circuit solutions and implements solutions that meet security and safety compliance for IP or SoC clocking.

• Defines SoC or subsystem level clocking targets and drives design teams to achieve these objectives as required.

• Build simulation models, drives physical implementation, conducts clock analysis, and supports power grid methodologies and implementation.

• Creates scalable flows for clocking infrastructure for better performance and power in the design.

• Interacts with architecture and IP/SoC design teams to understand clocking requirements and help them in deciding the right clock distribution methodology based on power and performance requirements.

• Proven track record of strong partnership and collaboration with managers, architecture, RTL design and other partner teams.

• In addition to the qualifications listed below, the ideal candidate will also have strong written and verbal communication skills.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• The candidate must have a Bachelor's degree in Computer or Electrical Engineering with 4+ years of industry experience -OR- a Master’s Degree in Computer or Electrical Engineering with 3+ years of industry experience.

• 3+ years of experience with SoC clocking architecture from PLL to partition implementation with Clock Tree Synthesis and have experience with industry standard clock distribution CAD tools such as Clock Builder.

Preferred Qualifications

• Experience as technical leader of SOC/ASIC designs responsible for physical clock design and convergence.

Experienced HireShift 1 (United States of America)Virtual US
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change. The application window for this job posting is expected to end by 09/15/2025