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Your responsibilities will include but not be limited to:
Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm microarchitecture specifications.
Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
Replicates, root causes, and debugs issues in the precision environment.
Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.
Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintains and improves existing functional verification infrastructure and methodology.
Coordinating and steering the efforts of multiple teams and team members.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 3+ years of relevant experience -OR- a Master's degree in Electrical/Computer Engineering or Computer Science and 2+ years of relevant experience -OR- PhD in Electrical/Computer Engineering or Computer Science
Preferred Qualifications
Experience in RTL Design validation experience developing unit or system level test-benches and test plan creation
Experience in Developing test-bench components such as monitors, scoreboard/checkers, and bus functional models (BFMs)
Experience in System Verilog Assertions and Functional Coverage
Experience in HDL such as Verilog and UVM/System Verilog
Experience in Scripting languages such as Perl/Python
Experience with working IP and SoC Verification teams and developing solutions spanning both requirements
Experience with Embedded Software/Firmware (C/C++)
Familiarity with hardware design flows (EDA) and tools: CDC, Lint, Synthesis, Logic Equivalence Checking, Timing
Experience withDeveloping/validatingCPU flows such as Reset, Power Management, and Boot flows
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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