Job Description:- Develop and master formal verification environments for control path and/or datapath designs.
- Collaborate closely with cross-geographical design and architecture teams to understand specifications and identify verification needs.
- Create and maintain formal models and properties for CPU components; analyze and debug verification failures, providing feedback and solutions to design teams.
- Guide and train team members in using formal tools and methodologies to successfully complete their verification assignments.
- Stay updated with the latest advancements in formal verification technologies and methodologies, integrating them into the team's workflow.
- Benchmark and develop new formal methodologies and tool flows to prove the correctness and reliability of complex digital circuits
Qualifications:- Master's degree in Electrical Engineering, Computer Science, or a related field, with 5-12 years of experience in formal verification.
- Strong understanding of digital design principles and CPU architecture.
- Proficiency in formal verification methodologies and tools such as JasperGold, VC-Formal, or equivalent.
- Extensive experience with hardware description languages (Verilog, VHDL) and formal verification languages (SystemVerilog Assertions, PSL).
- Excellent problem-solving and debugging skills, with effective communication and teamwork abilities.
- Proficiency in scripting languages such as Tcl, Python, or Perl is a plus
Experienced HireShift 1 (India)India, Bangalore
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.