Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification
Qualifications:Minimum Qualifications:
Bachelor's degree with 5+ years of experience in the verification of IPs
Hands on experience in applying formal property verification for Ips signoff at least for 3 years
Hands on experience in resolving convergence issues using FV on multiplies
Managing and Guiding juniors in their verification task, Stakeholder management.Preferred Qualifications:
Expertise in FV verification planning and strategies
Good understanding of FV tools and capabilities
Experienced HireShift 1 (India)India, Bangalore