What you'll be doing:
Developingphysical verification methodologies for implementation of graphics processors and SOCs.
Participate in developing physical verification flows for new technologies - DRC, LVS, Antenna flows - improving automation and expert workflows.
Work with design teams to improve overall DRC feedback and correlation improvement.
What we need to see:
BS/MSin Electrical Engineering or related field (or equivalent experience)
Minimum 4+ years of physical implementation experience with 2+ years in physical verification.
Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
Strong knowledge and experience with Physical Verification debug of shorts/compare results across DRC/LVS/Antenna related issues in both PV signoff tools as well as EDA implementation tools (ICC2/Innovus/other)
Direct experience with ICV and Calibre runsets for physical verification of DRC/LVS/Antenna.
Proficient in writing DRC/LVS rules, including advanced checks tailored to specific design requirements for ICV and CALIBRE tools.
Good scripting and programming skills in Python/Perl or other related automation languages.
Ways to stand out from the crowd:
Exposure to Virtuoso or ICWeb platforms , AI application to PV analysis or workflows, workflow automation experience.
You will also be eligible for equity and .
משרות נוספות שיכולות לעניין אותך