Nvidia Senior Physical Verification Engineer VLSI Implementation 

United States, Texas 

849314840

What you'll be doing:

• Responsible for support and debug of physical implementation GPU and SOC reticle-sized chips, coordinating with the PNR team to achieve SOL tape-out – including feedback recognition and correlation.

• Determining physical verification methodologies to improve workflow efficiency and timely issue detection. Integrate new workflows and checks into larger workflow automation systems.

• Participate in developing physical verification flows for new technologies - DRC, LVS, Antenna flows - improving automation and expert workflows.

• TSMC A16 rules and tape-out experience is preferred.

What we need to see:

• BS/MS in Electrical Engineering or related field (or equivalent experience)

• Minimum 4+ years of physical implementation experience with 4+ years in physical verification build and debug (can run concurrently).

• Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.

• Strong knowledge and experience with Physical Verification debug of shorts/compare results across DRC/LVS/Antenna related issues in both PV signoff tools as well as EDA implementation tools (ICC2/Innovus/other)

• Direct experience with ICV and Calibre runsets for physical verification of DRC/LVS/Antenna.

• Good scripting skills in Python/Perl or other related automation languages.

Ways to stand out from the crowd:

• Exposure to Virtuoso or ICWeb platforms , AI application to PV analysis or workflows, workflow automation experience.

• Proficient in writing DRC/LVS rules, including advanced checks tailored to specific design requirements for ICV and CALIBRE tools.

• Understanding of AI Chat and/or Agentive systems applied in the PV domain.