Intel Staff SOC DFT Engineer 

Malaysia, Penang 

912540424

Job Description:

• Lead the development and implementation of DFT methodologies for complex SOC designs, ensuring maximum test coverage and efficiency.
• Collaborate with cross-functional teams (design, verification, manufacturing) to define and optimize test strategies and requirements for new product designs.
• Manage and execute DFT tasks such as scan insertion, BIST (Built-In Self-Test), JTAG, boundary scan, and ATPG (Automatic Test Pattern Generation).
• Conduct in-depth fault simulation, scan chain analysis, and test pattern generation to verify and optimize design testability.
• Provide guidance, mentorship, and technical leadership to junior and mid-level DFT engineers, ensuring team members are aligned with industry best practices.
• Develop and maintain DFT-related automation tools to improve productivity and streamline the design process. Ensure designs meet testability requirements throughout the entire product lifecycle, from RTL to post-silicon validation.
• Work closely with manufacturing teams to ensure the testability of designs is optimized for production yield and cost.
• Perform detailed test coverage analysis and provide recommendations for test improvements to enhance product quality.
• Participate in design reviews, providing DFT expertise and insights to ensure design for manufacturability and testability.
• Contribute to the definition of DFT standards, methodologies, and workflows to drive consistency across the team and organization.
• Analyze and troubleshoot complex testability issues, providing clear and actionable solutions.
• Stay up-to-date with industry trends and advancements in DFT technologies, incorporating best practices into the team's processes.

Qualifications:

Minimum Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in DFT, SOC design, or related semiconductor design areas.
• Proven expertise in DFT techniques, including scan insertion, BIST, boundary scan, JTAG, fault simulation, and ATPG.
• Advanced knowledge of DFT tools such as Synopsys DFT Compiler, Mentor Tessent, Cadence Modus, or similar EDA tools.
• Proficiency in hardware description languages such as Verilog, VHDL, or SystemVerilog.
• In-depth experience with RTL design and verification processes and methodologies.
• Strong knowledge of semiconductor manufacturing processes and test flow.
• Expertise in leading and mentoring DFT engineering teams, with a focus on professional development and knowledge sharing.
• Excellent problem-solving skills with the ability to troubleshoot complex design and testability issues.
• Strong communication and interpersonal skills to effectively collaborate with cross-functional teams.
• Proven track record of driving process improvements and implementing efficient DFT solutions in large-scale projects.

Preferred Qualifications:

• Experience with advanced test techniques such as DFT for low-power and high performance SOC designs
• Familiarity with industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), IEEE 1500 (Core Test), and others
• Knowledge of Python or other scripting languages for automation.
• Experience with failure analysis, yield improvement and test cost optimization methodologies
• Experience with SOC (System on Chip) or complex multi-chip designs
• Experience in managing complex, high-visibility projects and working with senior leadership

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