Intel Staff SOC DFT Scan Engineer 

Malaysia, Penang 

638869376

Job Description:

We are seeking a highly experienced and visionary Staff/Senior SoC DFT (Design for Test) Scan Engineer to join our team. As a senior-level engineer, you will play a critical role in developing, leading, and optimizing DFT strategies for SoC designs. You will work closely with senior architects, design, verification, and manufacturing teams to create robust test solutions, drive DFT methodologies, and ensure the highest standards of testability in complex SoC designs.
In this role, you will lead the design and implementation of cutting-edge DFT solutions for advanced SoCs and be a key technical authority within the company, driving the direction of testability methodologies and best practices. Key responsibilities include:

DFT Strategy and Leadership:

• Lead and own the design and implementation of advanced DFT techniques, primarily focusing on scan-based testing, for cutting-edge SoC designs

• Define, develop, and improve comprehensive DFT methodologies, ensuring high-quality and efficient test coverage

• Provide technical leadership to cross-functional teams on DFT techniques and best practices, including scan insertion, fault simulation, and test pattern generation

• Establish DFT goals and metrics to ensure all designs are optimized for testability from the early stages of design

Scan Chain Insertion and Optimization:

• Architect and implement scan chain insertion methodologies, ensuring minimal design impact while achieving maximum test coverage and efficiency

• Optimize scan chains and test access mechanisms (TAM) to reduce test time and data volume, while maintaining high fault coverage

• Work closely with the RTL design and physical design teams to ensure seamless integration of DFT features into the design flow

Advanced Test Pattern Generation and Coverage:

• Oversee the generation of high-quality test patterns and ensure comprehensive fault coverage across all SoC blocks

• Analyze fault simulation and coverage reports to identify and implement optimization strategies for test patterns

• Develop and integrate advanced DFT techniques such as ATPG (Automatic Test Pattern Generation) for improved scan coverage

Tool Development and Automation:

• Lead the development and enhancement of custom DFT tools and automation flows to streamline the DFT process

• Implement automation strategies to improve scan insertion, test pattern generation, and fault simulation processes

• Drive tool evaluations and adopt state-of-the-art DFT tools and techniques to continuously improve team productivity and test efficiency

Cross-Functional Collaboration:

• Collaborate closely with the design, verification, test, and manufacturing teams to ensure the integration of DFT methodologies across the entire SoC lifecycle

• Act as the primary technical contact for all DFT-related matters within the organization, providing expert advice and support

• Lead and mentor junior DFT engineers, sharing knowledge and fostering a culture of continuous learning

Post-Silicon Support and Debugging:

• Provide post-silicon support for DFT validation, debug scan chain issues, and work on resolving any testability-related failures

• Lead debug efforts on scan and DFT-related issues, ensuring quick resolution and high-quality results in production

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Education:

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a related field. A Master's or PhD is a plus

Experience:

• Minimum 8 years of experience in SoC DFT engineering, with a proven track record in leading DFT initiatives for large, complex SoC designs
• Extensive experience with scan-based test methodologies, including scan insertion, fault simulation, and test pattern generation
• Proven experience in designing and implementing advanced DFT solutions for high-performance, multi-million-gate SoC designs
• Deep experience with DFT tools such as [Insert tools, e.g., Synopsys TetraMAX, Cadence Modus, Mentor Tessent] and understanding of tool integration into RTL design flows

Skills:

• DFT Expertise: Expertise in DFT methodologies, including scan insertion, test access mechanisms, fault simulation, ATPG, and low-power DFT techniques
• Tool Proficiency: Advanced knowledge of industry-standard DFT tools and EDA tools used for RTL synthesis, timing analysis, and simulation
• Scripting and Automation: Advanced proficiency in scripting languages (e.g., Python, TCL, Perl, Shell) to develop and optimize DFT automation flows
• RTL and Design Knowledge: Strong experience with RTL design in Verilog/VHDL and an understanding of SoC architectures and components (e.g., processors, memory, interfaces)
• Debugging and Optimization: Strong debugging skills to troubleshoot and resolve complex DFT-related issues, both pre-silicon and post-silicon
• Leadership and Mentoring: Experience leading DFT teams, providing technical leadership, and mentoring junior engineers
• Communication Skills: Excellent communication and interpersonal skills, with the ability to present complex technical concepts clearly to both technical and non-technical stakeholders

Desirable Skills:

• Knowledge of memory BIST (Built-In Self Test) and other advanced SoC testing methodologies
• Familiarity with advanced low-power design techniques and their impact on DFT
• Experience with post-silicon test and validation, including test coverage analysis and debug
• Familiarity with machine learning or AI techniques applied to DFT and test optimization is a plus

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research

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