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Job Description:
Responsibilities
Drive the test quality of the products from Design to Production
Participate/contributein silicon bring-up, characterization, and silicon test
Define and implement various DFx features
Requirements
Knowledge of Testability techniques and features (SCAN, Built-in-Self-Tests, Loop-Backs etc.) covering digital logic domain, embedded memories and PHY/IO’s
Scan flow development, ATPG pattern generation, verification and coverage analysis
Experience working with Mentor/Siemens DFT Tessent tool forscan/MBIST/bscan/IJTAGinsertion and verification
Experience working with Cadence DFT tools (Modus and Genus)
Well versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge
Strong knowledge of logic & circuit design fundamentals is needed
Working knowledge of TCL, perl
Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms
Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs etc..) is a plus
Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms is a must
Post Silicon experience in Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc. is a plus
Experience or familiarity in back-end chip design, Timing, CDC flows is a plus
Strong Pre/Post Silicon debugging, analytical and independent problem solving ability.
Must be a team player with good verbal and written communication skills.
Must be self-driven engineer with good project management and organizational skills to deliver high quality output in a timely manner.
Experience : Bachelors and 8+ years of related experience
Compensation and Benefits
The annual base salary range for this position is $119,000 - $190,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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