Broadcom DFT Engineer 

United States, California, San Jose 

765692230

KeyResponsibilities:

• Implement and verify DFT methodologies specifically for HBM, DDR and SerDes designs.

• Collaborate with design and architecture teams to identify and define critical testability requirements.

• Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.

• Analyze DFT-related data and provide insights for continuous design improvements.

• Document verification processes, results, and best practices to enhance team knowledge and efficiency.

• Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.

• Working closely with STA and DI Engineers design closure for test

• Generating, Verifying & Debugging Test vectors before tape release.

• Validating & Debugging Test vectors on ATE during the silicon bring up phase

• Assisting with silicon failure analysis, diagnostics & yield improvement efforts

• Interfacing with the customers, physical design and testengineering/manufacturingteams located globally

• Working closely with I/P DFT engineers & other stakeholders

• Debugging customer returned parts on the ATE

• Innovating newer DFT solutions to solve testability problems in 3nm IPs & beyond

• Automating DFT & Test Vector Generation flows

Skills/Experience:

• Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)

• Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.

• Understanding of DFT methodologies, including scan, BIST, and ATPG.

• Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).

• Excellent analytical and problem-solving skills.

• Strong communication and teamwork abilities.

• The ability toworkin a multi-disciplined, cross-department environment

• Solid knowledge in analog and digital circuit design, and device physics fundamentals

• Excellent problem solving, debug , root cause analysis and communication skills

• Experience working on ATE is a plus

• Familiarity with BIST logic for array and link testing is a plus

• Knowledge of AHB/APB/AXI buses is a plus

Education & Experience:

• Bachelors inElectrical/Electronic/ComputerEngineering and 8+ years of relevant industry experience or Masters Degree inElectrical/Electronic/ComputerEngineering and 6+ years of relevant industry experience