We need fast, focused verification engineers to adjust with the changing environment of the FPGA world while following best practices for high quality and sustainable code.
Your role and responsibilities
This role is responsible for leading and growing our Design Verification team. This includes defining and building benches for our designs from scratch, automating reporting as well as working with designers to find bugs to speed up the development cycle. Other responsibilities:
- Define the test plan and success criteria for verification of IP blocks
- Creatively solve verification requirements with the right tool i.e. UVM bench, System Verilog bench or lab testing with firmware testing.
- Creating the test benches and test cases to meet all verification requirements.
- Compare and articulate alternative approaches.
- Strong problem-solving skills and ability to direct the design team toward the problematic area of the design.
- Challenge the validity of given procedures and processes to enhance, improve and develop complementary adjustments and solutions.
- Utilize skills to apply Random/Deterministic Verification Principles and knowledge of engineering principles.
- Participate in overall departmental program planning.
- Influence the team’s budgetary and training responsibilities.
Required education
Bachelor's Degree
Preferred education
Bachelor's Degree
Required technical and professional expertise
- A minimum of 8 years of experience in Design Verification and System Verilog.
- A minimum of 8 years with writing UVM test benches and verifying coverage.
- Demonstrated communication skills in a high performing development environment.
- Self-Starter, ready to move quickly to keep the Design moving forward.
Preferred technical and professional experience
- Natural inclination for Verification and Testing.
- Experience with Cadence VManager.
- Driving projects with RTL/HW engineers.
- Experience with 3rd party IP blocks.
- Agile development.
- Python experience
