Cisco ASIC Verification Engineer 

United States, Massachusetts 

863999930

Your Impact:

As part of a growing Design Verification Team, you will work with other verification, DSP, and RTL engineers to ensure successful verification of complex ASICs throughout its pre-silicon lifecycle. You will work with C++ and UVM building test-benches and gathering and analyzing coverage reports. Responsibilities include:

• Develop detailed and comprehensive test plans.
• Develop verification test benches at block, inter-block, and chip levels.
• Apply innovative verification techniques to complex designs.
• Participate in the review of design verification coding and coverage metrics.
• Work collaboratively with the team to develop & incorporate the latest test technologies & processes.

Minimum Qualifications:

• Bachelor's degree and 5+ years of experience, or a Master's degree and 3+ years majoring in Computer Science, Computer Engineering, or Electronic/Electrical Engineering.
• Demonstrated experience in ASIC design verification methodologies and flows.
• Experience with C++ model co-simulation.
• Experience with HVL and HDL languages and tools, scripting and programming languages Verilog, SV, C++, Perl and/or Python.

• UVM experience is a plus
• Strong problem solving, communication, and team skills.
• Experience in object oriented programming.
• Networking knowledge is preferred, but not essential.

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