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Apple STA Synthesis Engineer United States, Texas, Austin 833653445
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Description
In this highly visible role you will be: - You will excel as you optimize designs to reach ground breaking power, area, timing goals.
Minimum Qualifications
- Bachelors Degree + 3 Years of Experience
Preferred Qualifications
- STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team.
- Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure.
- Embrace technical challenges with your natural passion to innovate.
- Ability to collaborate effectively with different functional teams and strong written/verbal communication.
- Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms.
- Professional experience with ECO implementation, both functional and timing closure.
- Familiarity with simulation, debugging tools, and working closely with DV team.
- Experience with multi-clock and multi-power domain designs.
- Familiarity with DFT insertion, and multi-mode timing constraints.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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