Qualcomm Synthesis/STA Engineer 

United States, California 

688396679

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. You will be a part of Qualcomm Connectivity organization responsible for the development of SoC designs.

Job responsibilities include RTL Synthesis using state of the art Physical Synthesis Tools; Timing Constraint development for Functional/Test Modes; Timing Constraints integration and validation for the SoC/Sub-Systems; Implement Low Power techniques in Implementation flows; Work with DFT teams to integrate Memory BIST, Scan for Blocks and Sub-Systems; Perform Power Aware Logic Equivalency checks; Run Static Low Power Checks for Isolation/Level Shifter implementations and analyze the results; Implementation of functional ECOs with the help of EDA tools and Validation; Analyze Dynamic and Leakage Power with low power design team and implement various optimization techniques to reduce power.

Support Design Verification to enable Gate Level Simulations, Timing Simulations and Power Aware Gate Level Simulations.

Educational Requirements:

Bachelor's, Electrical Engineering and/or Computer Engineering or equivalent experience Preferred: Master's, Electrical Engineering and/or Computer Engineering or equivalent experience

Preferred Qualifications:

• 5 years of experience in ASIC Implementation/Synthesis

• Strong Expertise with Synopsys/Cadence ASIC Synthesis tools and flows

• Experience with RTL Coding with Verilog and System Verilog

• Expertise with LEC/Formality Formal Verification tools, Functional ECO implementation and Validation

• Experience with UPF based implementation in Synthesis and PD flows

• Knowledgeable in clocking strategies and Create timing constraints for blocks and sub systems

• Strong Expertise with PrimeTime (PT) for PreLayout and PostLayout Static Timing Analysis

• Experience in Timing Closure with PrimeTime-ECO and/or Tweaker ECO Tools

• Exposure to RTL and Netlist based Power Estimations

• Experience with Memory BIST insertion and Simulations is a plus

• Automation skills with Tcl/Python/Perl/Linux scripting languages is a plus

• Good verbal and written communication skills

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$143,000.00 - $215,000.00