Nvidia Senior ASIC Physical Design Timing Engineer 

United States, California 

821253136

What you'll be doing:

• Drive timing closure work for DFT logic in our GPUs, CPUs, and SOCs at block cluster level and/or full chip level

• Work on all aspects of timing for DFT such as timing constraints, timing analysis, timing convergence, ECO implementation, and other checks

• Collaborate with DFT and the rest of the PD team to seamlessly move projects forward with new features and methodology improvements

What we need to see:

• Bachelor's Degree in Electrical or Computer Engineering (or equivalent experience)

• 5+ years of experience in Physical design/Timing

• Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence

• Expertise in physical design, optimization, and ECO implementation e.g. cell sizing, buffering, VT swap

• Hands-on knowledge of industry standard Timing/STA EDA tools

• Proficiency in programming and scripting languages, such as TCL, Python and Perl
  

Ways to stand out from the crowd:

• Experience with DFT timing closure for various modes e.g. scan shift, scan capture, transition faults, BIST, etc

• In-depth understanding of multiplexed scan logic and constraints

• Knowledge of clocking and clock controls in DFT modes

• Experience in methodology or flow development

• Great problem-solving skills, self-motivated