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Cisco ASIC DFT Technical Lead United States, California, San Jose 779365632
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience.
- Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Prior experience working with Gate level simulation, debugging with VCS and other simulators.
- Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- Scripting skills: Tcl, Python/Perl.
- Prior experience with Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
- Prior experience Test Static Timing Analysis
- Prior experience with Post silicon validation using DFT pattern
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