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Cisco ASIC DFT Technical Program Manager United States, California, San Jose 28220212
18.11.2024
The application window is expected to close by 12/20/2024
This is an onsite role and will require working out of the Milpitas/San Jose office location.
What You'll Do
- Work closely with DFT architecting leads to define and the DFT implementation specifications
- Responsible for closely managing the DFT implementation execution schedules, tracking status, dependencies and deliverable commitments
- Responsible for creating (collaborating with the team) and maintaining DFT checklist for different design phases, to ensure good quality
- The job requires the candidate to have the ability to collect and present and track DFT implementation status in an organized and easy to track manner
Who You'll Work With
You will be in the Silicon One development organization as an ASIC DFT Technical Program Manager in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases
with additional exposure to physical design signoff activities.
Minimum Qualifications:
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 8 years of experience
- Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan
- Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets
- Prior experience working with Gate level simulation, debugging with VCS and other simulators
- Prior experience with Scripting skills: Tcl, Python/Perl
Preferred Qualifications:
- Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- Prior experience with full chip DFT architecture, hierarchical testing, and high speed interface testing
We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).
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