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Apple SoC Physical Design Engineer PnR United States, Oregon, Beaverton 777718481
07.04.2025
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.
- Minimum BS and 3+ years of relevant industry experience.
- Experience with partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
- Experience with physical design construction and analysis flows and methodology.
- Ability to adhere to stringent schedule and die size requirements.
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
- Experience with sub 10nm tech nodes.
- Experience with industry standard tools, understanding their capabilities and underlying algorithms.
- Strong communication skills.
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