Marvell Senior Engineer Analog Layout 

United States, California 

751735903

What You Can Expect

The responsibilities include but not limited to.

• Improve the design methodology and flow.
• Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
• Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
• Provide the support to the product teams, for both pre and post silicon
• Test chip integration

What We're Looking For

• Master’s degree and/or PhD in Electrical Engineering, Computer Science or related fields and 7+ years ofexperience.
• Strong communication skills and a team player.
• Hardworking and motivated to be part of a highly competent design team.
• Proficient with fundamental concepts in digital logic design.
• Solid understanding of ASIC verification flows and methodologies.
• Experience with Verilog andSystemVerilog/SystemC/Vera.
• Strong skills in Perl and Tcl scripting.
• Proficient in UNIX Shell scripting (Csh, Bash).

Preferred skills:

• Formal verification.
• Low power design.
• MATLAB and C/C++ based system simulation and evaluation.
• DSP function hardware implementation knowledge.