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Apple Design Verification Engineer United States, North Carolina, Cary 744971150
31.03.2025
We are looking for a Design Verification Engineer who will enable bug-free first silicon for mixed-signal designs. The responsibilities include all phases of pre-silicon verification including, establishing design verification methodology, and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are encouraged to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, de-bug of the test failures. Develop block, IP and SoC level test-benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage.
- BS degree in technical discipline with minimum 3 years of relevant experience.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
- Deep knowledge of SystemVerilog test-bench language and UVM Experience developing scalable and portable test-benches
- Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations
- Experience with serial protocols such as PCIe or USB Experience with mixed signal verification methodology for IPs such as PHYs, PLLs etc.
- In lieu of UVM knowledge, C/C++ level knowledge
- Deep knowledge of one of the scripting languages: Python, Perl, TCL
- Deep knowledge of formal verification methodology
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