Required/Minimum Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
- 4+ years of experience in production design tape outs & implementing PPA (Power, Performance and Area) solutions with deep understanding of E2E DFT-Functional Timing Analysis & Convergence Physical Design domain.
Other Qualifciations:
The ability to meet Microsoft, customer and/or government security screening requirements is required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
- Extensive experience in large-scale SoC, CPU, and IP design tape-outs utilizing advanced foundry process nodes.
- Deep expertise in DFT-Physical Design (PD) architecture, including DFT modes and methodologies, with comprehensive experience in Static Timing Analysis (STA) for complex hierarchical SoC/CPU designs.
- Expertise in Engineering Change Order (ECO) implementation for power/timing convergence. Solid grasp of Timing (Functional and DFT) ECO closure methodologies is essential.
- Collaborate closely with Physical Design engineers to proactively identify and address DFT and functional architectural challenges, clocking strategies, global bus planning, and RTL/architecture feedback across various milestones.
- Proficient in understanding functional and DFT constraints, performing STA, driving timing optimization, and achieving timing closure.
- Thorough understanding of design trade-offs across power, performance, and area (PPA).
- Hands-on experience with industry-standard EDA tools such as Synopsys, and Cadence tool suites.
- Partner effectively with PD, DFT, STA flow, CAD teams, and EDA tool vendors to ensure seamless integration and execution.
- Demonstrated ability to take full ownership of individual deliverables while contributing collaboratively across teams.
- Proven track record in mentoring, cross-functional collaboration, and influencing teams through clear and effective communication.
- interpersonal skills with a commitment to fostering diverse and inclusive team environments.
- Exceptional problem-solving and data analysis capabilities.
- Proficient in automation and scripting using languages such as Perl, TCL, and Python.
- Great communication, collaboration and teamwork skills and ability to contribute to D&I
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until July 25th, 2025.