For wireless system, power amplifiers (PA) in the transmitter are the main source of power consumption. To improve efficiency, PA must be designed beyond the classic class-AB, together with enhancement using envelope tracing, or envelope elimination and restoration (EER, or polar transmitter). Those designs come with impairments or nonlinear distortion that need to be clean up using digital signal processing (DSP) techniques. RF/analog architectures with the help of DSP, their optimizations and calibrations are the critical technique to achieve such high performing systems. In this technical role, you will be at the center of a silicon design group responsible for using digital algorithm or method to improve the PA efficiency, reducing power consumption, but with acceptable linearity for high data rate applications. You will mainly work on architecting various calibration and correction methods for implementation in hardware/firmware and validation of overall performance enhancement through lab measurement. You will interact with RF/analog designers, software or firmware engineers, digital designers, product engineers and architects to define and specify parts in the wireless systems. You will also get to work with digital designers and firmware designers to realize these methods with power and area efficient digital implementations with high efficiency software implementations, and possibly with hardware acceleration. And to bring up, test, characterize, and optimize real silicon in lab to the production qualities.