Intel Analog Platform Architect 

United States, Oregon, Hillsboro 

710584085

Delivers signal integrity solutions for large, complex highspeed platforms, boards, and packages. Develops a viable space for all interconnects including 2D and 3D models extracts of electrical structures for the entire dietodie interconnect. Defines signal integrity rules, reviews implementation, documents characterization and measurement reports, and improves and optimizes design margins. Applies knowledge of signal integrity design and tradeoffs to perform simulations of interconnect and guide package and platform physical implementation, and designs and characterizes test structures to correlate simulations and measurements for interconnects using intricate highspeed equipment and debugs challenges. Develops electrical specifications and new industry standard interconnect specifications to guide consortiums for nextgeneration interfaces. Documents and provides implementation guidelines to the end customers as part of the platform design guide. Collaborates with IP design teams and silicon integration teams to ensure the IP and SoC designs maximize the platform level solution space to meet targeted product landing zone requirements and minimize quality degradation (e.g., attenuation, crosstalk, jitter, power noise) and cost. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market. Conducts feasibility studies and works with development teams to deliver system End to End Electrical solutions. Defines power delivery, signal integrity, and power integrity targets, architects platform solutions meeting them, and ensures delivery to the end customer as part of the platform design guide. Collaborates with the SoC, platform, power, IO, and interconnects teams to create and define power sequencing requirements, platform power, and signal path requirements for Memory DDR/LP technologies.

Must have MS in Electrical Engineering with 12+ years or B.Tech in Electrical/Electronics Engineering with minimum 14+ years' experience with below skill sets:Strong electrical/electromagnetic fundamentals.Dealing with complexity, analyzing information and driving platform electrical issues for closure.Hands on experience in EV/system or board design and process.Excellent background in High Speed System Interfaces like DDR, PEG, USB3.0 etc.Working knowledge of basic electronic equipment including digital oscilloscope, DMM, network analyzer etc.Familiar with PCB design tools, including Allegro, Mentor PCB and exposure to UNIX.Exceptional leadership record.Excellent leadership, communication (written, verbal and presentation) and interpersonal skillsBuild and maintain relationships by engaging business leaders to establish credibility, solve problems, build consensus and achieve objectivesProven ability to work creatively and analytically in a problem-solving environment demonstrating teamwork, innovation and excellenceStrong leadership, diplomatic and motivational skills including the ability to lead up, across and down multiple business and technology organizationsExperience working both independently and in a team-oriented, collaborative environmentTechnically competent with strong Platform Electrical and Analog backgroundRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits Annual Salary Range for jobs which could be performed in the US $186,760.00-$299,166.00*Salary range dependent on a number of factors including location and experienceThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.