In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.
Minimum BS and 3+ years of relevant industry experience.
Ability to adhere to stringent schedule and die size requirements.
Experience with partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
Knowledge of physical design construction and analysis flows and methodology.
Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
Experience with sub 10nm tech nodes.
Experience with industry standard tools.
Strong communication skills.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.