Amazon Senior DSP Wireless Systems Engineer Digital RF 

United States, California, San Diego 

645301036

Job summaryThe Role:
As a Senior DSP Engineer working in the Digital RF Systems team, you will be responsible for DSP architecture definition, design and simulation of DSP blocks in wireless communication SOC that are used in Kuiper phased array systems. You will be implementing end-to-end system models including fixed point DSP blocks, RF impairments of the radio, phased array antenna and satellite channel. You will be involved in novel techniques to estimate and correct RF impairments that will be implemented in HW and FW. Based on the system level constraints such as low power and cost, you will develop optimized solutions to support high throughput for our customers.
As a Senior DSP Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with internal inter-disciplinary teams such as ASIC/RFIC designers, FW/SW engineers, design verification engineers. You will drive key aspects of the silicon design, validation and optimization in the lab.In this role you will:
· Design and model DSP algorithms such as beamformer, DPD, CFR, digital cancellation schemes and RF impairment compensation blocks
· Model RF transceivers impairments and develop RF impairment compensation algorithms. Develop and optimize HW/SW calibration methods for RF SOC and phased array systems
. Architect HW and FW partitioning of calibration algorithms
. Develop detailed test plans and test procedures for validation and characterization of RF Wireless SOC performance. Characterize and enhance RF performance of the wireless SOC and help integration of the silicon into Kuiper phased array systemsExport Control Requirement:

· 8+ years of relevant experience in wireless DSP/RF systems engineering (LTE, 5G-NR, WiFi 802.11, BLE)
. In depth knowledge of DSP design for low power consumption ASIC
. Hands on MATLAB, Python and/or C/C++ for DSP algorithm development, modeling and simulation
. Good understanding of RF blocks and components
. Experience in RF impairment estimation and compensation techniques
. Working knowledge of FW implementation of various DSP algorithms
. Hands on experience in using lab equipment, bring-up and validation of chip
· MSEE/PhD is highly preferred

. Strong background in Communication Theory (signal estimation and detection, AGC, channel estimation), OFDM, MIMO, Digital/Wireless Communication Systems and engineering
. Extensive experience in designing low power/area digital signal processing blocks for Wireless RF SOCs
. Excellent understanding of RF architectures and blocks used in the Wireless SOCs
· MATLAB, Python, C++ experience with emphasis on fixed point modeling of DSP blocks, RF impairment modeling, RF calibration algorithm development, system performance simulations (EVM, ACRL, OOB emissions)
. Experience with bit-accurate modeling to match RTL implementations, emulations, FW development
. Familiarity with phased array systems and phased array performance optimization techniques
. Experience in silicon bring-up in the lab and using lab equipment such as vector spectrum analyzer, signal generators, high speed scopes and logic analyzers