Amazon Sr Physical Design Engineer Annapurna Labs 

United States, California, Cupertino 

6388007

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.Key job responsibilities
- Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure
- Drive IO/Core block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off
- Develop physical design methodologies
- Evaluate 3rd party IP and provide recommendations

- BS + 8yrs or MS + 6yrs in EE/CS
- 6+ years of experience in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm
- Block Design using EDA tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
- Deep understanding on sign-off activities (timing, ir/em, physical verification)
- Scripting experience with Tcl, Perl or Python

- Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
- 4+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain.
- Thorough knowledge of device physics, custom/semi-custom implementation techniques
- Experience solving physical design challenges across various technologies such as DDR, PCIe, fabrics etc.
- Experience in extraction of design parameters, QOR metrics, and analyzing trends
- Ability to provide mentorship, guidance to junior engineers and be a very effective team player
- Meets/exceeds Amazon’s leadership principles requirements for this role
- Meets/exceeds Amazon’s functional/technical depth and complexity for this role