Amazon Sr Physical Design Methodology Engineer Annapurna Labs 

United States, California, Cupertino 

840954053

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.Key job responsibilities
Define, develop and deploy innovative physical design methodologies (RTL2GDS) and CAD flows for ML Accelerator chips in advanced nodes
Drive improvement in RTL2GDS flows/methodology for PPA and TAT improvements
Create Dashboard and Central reports for project tracking and visualizing QoR/stats
Fine tune cloud infrastructure to improve turnaround times for physical design work.Work with EDA tool vendors to evaluate new methods, solve bugs, improve usability, etc.
Drive setting up RTL2GDS flows for new nodes, run regressions, quality assurance checksAbout the team
About the teamDiverse Experiences
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- BS + 10yrs or MS + 7yrs in EE/CS
- 5+ years of experience in developing physical design methodology or CAD flows in synthesis, PNR, and sign-off areas for advanced technology nodes.
- Proficient in programming/scripting languages (Perl, Python, C++)
- Solid understanding of ASIC physical design, and methodologies including synthesis, place and route, STA, IR, formal and physical verification.
- Demonstrated level of expertise in PD tools such as Innovus, ICC2, Fusion Compiler, STA, and Sign-Off.
- Proven track record of delivering metric driven PPA flow development and support.