המקום בו המומחים והחברות הטובות ביותר נפגשים
What you will be doing:
We support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches).
Bring up GPUs, SOCs, Switch, NIC on emulation, root causing system level test fails and emulator environment issues.
Bring-up and verify High Speed protocols likePCIe/CXL/NVLINK/IB/Ethernetetc …. Low speed protocols like I2C/I3C/SPI/UART
Bring-up/debug issues related to CPU and GPU Coherency
We have continual collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams.
Work constructively leading emulation vendors to debug issues using various tools.
Write monitors and checkers that aid debug in HW test issues and FW/SW bring-up
What we need to see:
M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field.
8+ years of proven experience.
Individual should be proficient in Verilog and/or VHDL, C/C++ and SystemVerilog.
Must have: Protocol knowledge of at least one of the High-speed interfaces:PCIe/CXL/NVLINK/IB/Ethernetetc ….
Good to have: Low-speed protocols like I2C/I3C/SPI/UART and BMC interaction in server platforms
Working Knowledge of CPU - GPU coherency
Experience with UVM verification environments and scripting with Perl, Python and C/C++ is essential.
Be familiar with hierarchical design approach, top-down design, SoC and system level verification.
Candidates will be working on-site at our Santa Clara, CA location.
You will also be eligible for equity and .
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