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Google Silicon Layout Engineer United States, California, Fremont 594404119
20.11.2024
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 8 years of experience with analog circuit design principles and layout techniques.
- Experience with industry-standard layout tools (e.g., Cadence Virtuoso, Mentor Graphics Calibre).
- Experience with advanced process nodes (22nm and below) and associated design challenges.
Preferred qualifications:
- Experience with scripting languages (e.g., Python, TCL) for layout automation.
- Knowledge of parasitic extraction and analysis.
- Familiarity with various layout verification tools and methodologies.
- Familiarity with reliability and manufacturability considerations.
- Strong communication and teamwork abilities.
- Excellent problem-solving and analytical skills.
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