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RESPONSIBILITIES:
2 or more years experience with Cadence APD, SiP, or equivalent package layout CAD tool (3 or more years is preferred)
Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
Schedule, prioritize, & track your work across 2+ projects simultaneously
General flip-chip BGA package design & engineering
Contribute to efficiency improvements for the design group
EDUCATION/EXPERIENCE & REQUIREMENTS:
BSEE or similar field and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
Knowledge of package-level signal integrity and power integrity, to apply to package designs
Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
Self-management and organization skills
Compensation and Benefits
The annual base salary range for this position is $107,000 - $190,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
משרות נוספות שיכולות לעניין אותך