Cisco Hardware Engineer 

Armenia, Yerevan 

582081751

• Conduct synthesis at the block level.
• Perform block-level place and route.
• Implement block-level Static Timing Analysis (STA).
• Generate and integrate timing ECOs at the block level.
• Ensure block-level physical verification is complete and accurate.
• Analyze block-level Electromigration and IR Drop (EMIR).
• Implement low power checks to ensure energy-efficient designs.
• Carry out formal verification to validate design correctness.
• Actively participate in review discussions, providing insightful feedback and suggestions.

• Expert-level knowledge of CMOS basics and semiconductor devices
• Comprehensive experience in Full Chip - Netlist to GDSII Implementation , encompassing Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, STA, Power Integrity Analysis, Physical Verification, and Chip Finishing.
• Desired knowledge of Physical Design Methodologies, along with hands-on experience or academic familiarity with advanced sub-micron technologies (7nm, 5nm, etc.).
• A strong grasp of Physical Design methodologies, complemented by a proactive approach to applying practical insights using Physical Design Tools and Flows to streamline design cycles.
• While proficiency in Tcl programming is advantageous, it is not a prerequisite. However, candidates should exhibit a willingness to learn and employ Tcl scripting to automate design tasks and improve process efficiency.

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