Cisco Senior RTL Design Engineer 

Armenia, Yerevan 

293025374

You will be in the Silicon One development organization as a senior DFT verification lead in Armenia. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.

• Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification.
• Sub-system/SoC integration and verification.
• Review/enhancement of RTL codes.
• Improve flows and methodologies to streamline IP/SoC development and integration.
• Work closely with the verification team for complex debugs to resolve verification failures.
• Close interaction with physical design team to reach better physical design QoR.

• 7+ years of industry experience in ASIC digital design.
• Proficient in Verilog/System Verilog coding.
• Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
• Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.
• Ability to write scripts using Python, Tcl, Make.
• Good communications skills, self-motivated and well-organized.

• Familiarity with power optimization techniques , power intent (UPF), power estimation.
• Familiarity with DFT/MBIST is a plus