Cisco Physical Verification Engineer 

Armenia, Yerevan 

969781960

Perform full-chip physical verification tasks, including DRC, LVS, ERC, and ANT checks, ensuring signoff-clean results.

Debug and resolve physical verification issues at both block and chip levels, working closely with implementation teams and IP developers.

Collaborate with block and TOP-level implementation teams to provide feedback on physical design updates.

Deploy and enhance physical verification flows and methodologies, including the development of custom checks for robust verification.

Support block and chip-level teams in resolving local physical verification challenges.

5+ years of experience in TOP-level physical verification, including debugging and providing solutions for DRC, LVS, ERC, and ANT issues.

Strong expertise in deep submicron CMOS/FinFet technologies and experience with relevant processes.

Solid understanding of physical verification and signoff methodologies.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.

Excellent verbal and written communication skills in English.

Comprehensive understanding of the full physical design cycle from RTL to GDSII.

First hand experience with ASIC implementation and verification workflows.

Proficiency in scripting languages such as Python, Tcl, or Shell for automation and efficiency improvements.