Amazon Sr Mixed-Signal Silicon Engineer 

United States, Washington, Redmond 

455531684

The Role:
As Senior Mixed-Signal Silicon Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third-party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment.As a member of the RFIC team, you will be responsible for the architectural definition, design, simulation, layout, and extracted simulation for transmit and receive mixed-signal circuit blocks including data converters and aspects of SERDES. Strong focus will be on creating power and cost optimized solutions for a given system performance.Export Control Requirement:
Key job responsibilities
 Explore architectures for DACs/ADCs, DLLs, and other timing circuits/signal converters and make detailed presentations on power/area/performance trade-offs.
 Design & optimize high-speed >800Msps medium resolution (5-8 bits) DACs & ADCs in deeply scaled CMOS processes.
 Analyze and design key circuit blocks for high-speed SERDES interfaces.
 Perform circuit layout, parasitic extraction, and run extracted simulation across various corners to make sure designs are robust and can be taken to volume production.
 Collaborate with the digital design team to define analog/digital boundary requirements for circuit calibration, clock generation, and timing.
 Specify bench and production test plans for your designs.Redmond, WA, USA

 Master’s / PhD degree in Electrical / Communications Engineering or related field.
 7+ years of experience in mixed-signal design, preferably in an advanced node.
 Proven track record where products have gone to volume production.

 10+ years of hands-on experience in low-power mixed signal circuit design.
 Strong technical background in some of the following:
o Mixed-signal design, layout and verification in FinFET, SOI, BiCMOS, and Bulk CMOS technologies.
o Radio sub-system design (ADCs, DACs, PLLs, etc). Strong knowledge of architectural optimizations including pipe-lining/time-interleaving.
o Solid understanding of analog design and layout techniques (bias, matching) as well as clock distribution.
o Proficiency with digital and mixed signal simulators, for example Incisive/Xcelium, VCS, AMS Designer, or CustomSim-VCS.
o Strong ability to solve simulation accuracy, speed and capacity issues.
o Strong understanding of the implementation of high-level, mixed signal, and behavioral models for such circuits.
o Efficient programming and software development skills in Python, Perl, and SKILL.
o Knowledge of the Cadence Virtuoso Design Framework, Virtuoso Schematic Editor, and Analog Design Environment (Explorer/Assembler), including flow automation and custom netlisting with SKILL.
 Strong written and verbal skills.